Semiconductor devices formed on a substrate, commonly referred to as “chips”, are often times encapsulated during the assembly process in order to protect the devices from external environmental influences. For example, during assembly, the chips are commonly coated with an epoxy molding compound (EMC), which serves as a physical barrier for the chip. However, such EMC configurations are known to be a source of mechanical stress that is incident on the chips. For this reason, prior to formation of the EMC, the upper surface of a chip is covered with a polyimide layer during fabrication, which serves to alleviate the mechanical stress.
The polyimide layer further serves to prevent nearby energized particles from entering the chip, which could have an adverse effect on data stored in the chip, or otherwise affect chip operation. For example, the polyimide layer prevents alpha particles from penetrating the chip devices, thereby reducing the soft error rate (SER) of the chip, which otherwise might be increased by entry of the particles into storage capacitors of the chip.
To simplify the process of depositing and placing the polyimide layer, photosensitive polyimide layers (PSPLs) have become popular. Such photosensitive layers have the exposure properties of general photoresist layers, and therefore are readily adaptable to fabrication processes that rely on photolithography for depositing layers of material.
FIGS. 1 and 2 are cross-sectional views of a conventional fabrication method of a semiconductor device utilizing a PSPL. In the figures, M represents an internal circuit region of a device, and P represents a bonding pad region of a device.
In FIG. 1, an inter-layer dielectric (ILD) layer 13 is formed on a semiconductor substrate 11. A bonding pad 15 is formed on the ILD 13 in the pad region P. A passivation layer 17 is formed on the resultant structure, in both the circuit region M and in the pad region P. The passivation layer 17 comprises, for example, a single layer of silicon nitride or a combined silicon nitride and silicon oxide layer. Following this, a PSPL layer 19 is formed on the passivation layer 17, for example to a depth on the order of 68,000 Å.
In FIG. 2, the resulting structure is selectively exposed to light using a photo mask to form a vertical opening over the bonding pad 15. As a result, a region 19n of the PSPL 19 above the bonding pad 15 is properly exposed. However, during exposure, a portion of the light can stray to improperly irradiate other regions of the PSPL, leading to unwanted exposure regions 19a in other locations of the structure. This is caused, for example, by internal reflection and/or diffraction of the light within the exposure apparatus, such as a stepper apparatus, containing the photo mask. The resulting structure is then developed, using a developing step, to remove the properly exposed region 19n of the PSPL; however, the improperly exposed region 19a is also developed and removed during this step.
Following this, the passivation layer 17 is etched using the developed PSPL layer 19 as an etch mask, exposing the underlying bonding pad 15. The exposed bonding pad 15 is then electrically connected to a package pin, for example, using a wire bonding technique.
The improperly exposed region 19a′ corresponds to a barcode pattern, or mask alignment key pattern of the photo mask. This is referred to in the art as a “ghost image”. The thickness of improperly exposed region 19a can be on the order of 1000 Å, or deeper. As a result, the PSPL layer 19 has an uneven thickness in the improperly exposed region 19a. With the continuing trend toward ever-higher integration of semiconductors, there is a need for thinner PSPL layers 19, for example, on the order of 30,000 Å. However, as the PSPL layer becomes thinner, the depth of the ghost image 19a becomes more and more significant, leading to proportionally greater thickness variation in the PSPL layer 19. This results in a higher likelihood of cracking in the PSPL layer, which corresponds directly with an increase in the device soft error rate (SER).
During exposure of the PSPL, any refracted or reflected light that is a source of the ghost images 19a has a lower energy than the direct light that properly exposes the region 19n above the bonding pad 15. Nevertheless, the refracted or reflected light still has an energy level that is high enough to expose the ghost image regions 19a in the PSPL. This is because the PSPL layer 19 has relatively poor photosensitivity as compared to conventional photoresist. This comparison is depicted in FIG. 3.
FIG. 3 is a plot of development rate R as a function of exposure energy level E. Curve 1 represents exposure characteristics of the conventional photoresist material, and curve 2 represents exposure characteristics of the PSPL layer 19. As can be seen in the plot, the PSPL (curve 2) exhibits a faster development rate than the conventional photoresist (curve 1) at energy levels below the critical energy Ec level, which is the level of exposure energy required for normal exposure of the layer. At levels less than Ec, generated for example, by reflected energy, a PSPL layer is exposed more rapidly than conventional photoresist materials, and is therefore more sensitive to stray exposure energy, for example, reflected and diffracted exposure energy.
Japanese laid-open patent number 2001-94056 discloses a method of fabricating a semiconductor device using a PSPL. In this approach, a passivation layer is formed on an underlying substrate that includes a bonding pad. A PSPL layer is formed on the passivation layer, and a photoresist layer, approximately 5000 Å in thickness, is sequentially formed on the PSPL layer. An exposure process is performed to expose regions of the photoresist layer and the PSPL layer above the bonding pad. The exposed regions of the photoresist layer and the PSPL layer are developed to form a via hole that exposes the passivation layer above the bonding pad. The passivation layer above the bonding pad is then etched using the photoresist layer as an etching mask, exposing the bonding pad. Following this, the upper photoresist pattern is removed, and the bonding pad is wire-bonded to a package pin.
In this example, due to the thickness of the photoresist layer, the exposure time increases proportionally, and therefore the energy for exposing the photoresist layer and the PSPL layer is considerably higher than that required for conventional photolithography processes. Lengthening of exposure time and increase in the exposure energy can cause a degradation of process throughput and increase the likelihood of pad open failure in the subsequent etching process. In addition, since the photoresist pattern is removed only after exposing the underlying bonding pad, it is difficult to remove the relatively thick photoresist pattern without causing damage to the underlying PSPL and the exposed pad during the removal process.